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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad7827 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 3 v/5 v, 1 msps, 8-bit, serial interface sampling adc functional block diagram features 8-bit half-flash adc with 420 ns conversion time 200 ns acquisition time 8-lead package on-chip track-and-hold on-chip 2.5 v reference with 2% tolerance operating supply range: 3 v 6 10% and 5 v 6 10% specifications @ 3 v and 5 v dsp/microcontroller compatible serial interface automatic power-down at end of conversion input ranges 0 v to 2 v, v dd = 3 v 0 v to 2.5 v, v dd = 5 v general description the ad7827 is a high speed, single channel, low power, analog- to-digital conv erter with a maximum throughput of 1 msps that operates from a single 3 v or 5 v supply. the ad7827 contains a track/hold amplifier, an on-chip 2.5 v reference (2% toler- ance), a 420 ns 8-bit half-flash adc and a serial interface. the serial interface is compatible with the serial interfaces of most dsps (digital signal processors). the throughput rate of the ad7827 is dependent on the clock speed of the dsp serial interface. the ad7827 combines the convert start and power down signals at one pin, i.e., the convst pin. this allows a unique automatic power-down at the end of a conversion to be imple- mented. the logic level on the convst pin is sampled at the end of a conversion and, depending on its state, the ad7827 powers down. the ad7827 has one single-ended analog input with an input span determined by the supply voltage. with a v dd of 3 v, the input range of the ad7827 is 0 v to 2 v and with v dd equal to 5 v, the input range is 0 v to 2.5 v. the parts are available in a small, 8-lead, 0.3" wide, plastic dual-in-line package (dip) and an 8-lead, small outline ic (soic). product highlights 1. fast conversion time the ad7827 has a conversion time of 420 ns. faster conver- sion times maximize the dsp processing time in a real time system. 2. built-in track-and-hold the analog input signal is held and a new conversion is initi- ated on the falling edge of the convst signal. the convst signal allows the sampling instant to be exactly controlled. this feature is a requirement in many dsp applications. 3. automatic power-down the convst signal is sampled approximately 100 ns after the end of conversion and depending on its state the ad7827 is powered down. 4. an easy to use, fast serial interface allows direct interfacing to most popular dsps with no external circuitry. buf t/h 2.5v ref 8-bit half-flash adc serial port control logic v dd detect rfs d out sclk convst gnd v dd v refin /v refout v in comp ad7827
C2C rev. 0 ad7827Cspecifications (v dd = +3 v 6 10%, v dd = +5 v 6 10%, gnd = 0 v, v refin/refout = 2.5 v. all specifications C40 8 c to +105 8 c unless otherwise noted.) parameter version b units test conditions/comments dynamic performance f in = 30 khz; f sample = 1 mhz signal-to-(noise + distortion) ratio 1 48 db min total harmonic distortion 1 C55 db max peak harmonic or spurious noise 1 C55 db max intermodulation distortion 1 fa = 29.1 khz; fb = 29.9 khz 2nd order terms C65 db typ 3rd order terms C65 db typ dc accuracy resolution 8 bits integral nonlinearity (inl) 1 0.5 lsb max differential nonlinearity (dnl) 1 0.5 lsb max offset error 1 1.5 lsb max gain error 1 2 lsb max minimum resolution for which no missing codes are guaranteed 8 bits analog input 2 input voltage range 0 v min v dd = 5 v 2.5 v max 0 v min v dd = 3 v 2 v max input leakage current 1 m a max input capacitance 10 pf max reference input v refin / refout input voltage range 2.55 v max 2.45 v min input current 1 m a typ 50 m a max logic inputs convst , sclk v inh, input high voltage 2.4 v min v dd = 5 v 10% v inl, input low voltage 0.8 v max v dd = 5 v 10% v inh, input high voltage 2.0 v min v dd = 3 v 10% v inl, input low voltage 0.4 v max v dd = 3 v 10% input current, i inh 1 m a max typically 10 na, v in = 0 v or v dd input capacitance 10 pf max logic outputs d out , rfs v oh, output high voltage i source = 200 m a 4 v max v dd = 5 v 10% 2.4 v min v dd = 3 v 10% v ol, output low voltage i sink = 200 m a 0.4 v max v dd = 5 v 10% 0.2 v min v dd = 3 v 10% high impedance leakage current 1 m a max high impedance capacitance 15 pf max conversion rate conversion time 420 ns max track/hold acquisition time 200 ns max
C3C rev. 0 ad7827 timing characteristics 1, 2 (v refin/refout = 2.5 v, all specifications C40 8 c to +105 8 c, unless otherwise noted) parameter 5 v 6 10% 3 v 6 10% units conditions/comments t convert 420 420 ns max conversion time. t 1 20 20 ns min minimum convst pulsewidth. t 2 t convert +t 3 t convert +t 3 ns min falling edge of convst to falling edge of rfs. t convert +t 3 +t 7 +t 8 t convert +t 3 +t 7 +t 8 ns max t 3 3 14 18 ns max rising edge of sclk to falling edge of rfs. t 4 14 18 ns max rising edge of sclk to rising edge of rfs. t 5 3 20 20 ns max rising edge of sclk to high impedance disabled. t 6 3 14 18 ns max rising edge of sclk to d out valid delay. t 7 25 25 ns min minimum high sclk pulse duration. t 8 25 25 ns min minimum low sclk pulse duration. t 9 4 20 20 ns min bus relinquish time after sclk falling edge. 35 35 ns max t 10 20 20 ns max maximum delay from falling edge convst to rising edge rfs if rfs reset by convst . t 11 30 30 ns min minimum time between end of serial read and next falling edge of convst . t power-up 11 m s max power-up time from rising edge of convst using external 2.5 v reference. t power-up 25 25 m s max power-up time from rising edge of convst using on-chip reference. notes 1 sample tested to ensure compliance. 2 see figures 13, 14 and 15. 3 measured with the load circuit of figure 1 and defined as the time required for an output to cross 0.8 v or 2.4 v with v dd = 5 v 10% and time required for an output to cross 0.4 v or 2.0 v with v dd = 3 v 10%. 4 derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 1. the measured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the time, t 9 , quoted in the timing characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances. specifications subject to change without notice. c l 50pf to output pin i ol i oh 200 m a 200 m a +2.1v figure 1. load circuit for digital output timing specifications parameter version b units test conditions/comments power supply v dd 4.5 v min 5 v 10% for specified performance 5.5 v max 2.7 v min 3 v 10% for specified performance 3.3 v max i dd normal operation 10 ma max 8 ma typically power-down 1 m a max logic inputs = 0 v or v dd power dissipation v dd = 3 v normal operation 30 mw max typically 24 mw power-down 200 ksps 9.58 mw max 1 msps 47.88 mw max notes 1 see terminology section of this data sheet. 2 refer to the analog input section for an explanation of the analog input(s). specifications subject to change without notice.
ad7827 C4C rev. 0 warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7827 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. pin function descriptions pin no. mnemonic description 1 convst convert start. puts the track-and- hold into hold mode and initiates a conversion. the state of this pin at the end of conversion also determines whether or not the part is powered down. 2v in analog input is applied here. 3 rfs receive frame sync. this is an output. when this signal goes logic high at the end of a conversion, the dsp starts latching in data on the next cycle of sclk. 4 gnd ground reference for analog and digital circuitry. 5v ref reference input. 6d out serial data is shifted out on this pin. data is clocked out by the rising edges of sclk. 7 sclk serial clock. an external serial clock is applied here. the clock must be continuous so the rfs (frame sync) can be synchronized to the clock for high speed data transfers. (see microprocessor interfacing section.) 8v dd positive supply voltage 3 v/5 v 10%. pin configuration top view (not to scale) 8 7 6 5 1 2 3 4 convst v in rfs v dd sclk d out v ref gnd ad7827 absolute maximum ratings* v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v digital input voltage to gnd ( convst , sclk) . . . . . . . . . . . . . . C0.3 v, v dd + 0.3 v digital output voltage to gnd (d out , rfs) . . . . . . . . . . . . . . . . . . . C0.3 v, v dd + 0.3 v v ref to gnd . . . . . . . . . . . . . . . . . . . . . . C0.3 v, v dd + 0.3 v analog input voltage to agnd . . . . . . C0.3 v, v dd + 0.3 v operating temperature range industrial (b version) . . . . . . . . . . . . . . . C40 c to +105 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . +300 c plastic dip package, power dissipation . . . . . . . . . . 450 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . +105 c/w lead temperature, (soldering 10 sec) . . . . . . . . . . +260 c soic package, power dissipation . . . . . . . . . . . . . . . 450 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . +75 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220 c esd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0 kv *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide linearity error package package model (lsb) description option ad7827bn 0.5 lsb plastic dip n-8 ad7827br 0.5 lsb small outline ic so-8
ad7827 C5C rev. 0 terminology signal-to-(noise + distortion) ratio this is the measured ratio of signal-to-(noise + distortion) at the output of the a/d converter. the signal is the rms amplitude of the fundamental. noise is the rms sum of all nonfundamental sign als up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the q uantiza- tion noise. the theoretical signal-to-(noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal-to- ( noise + distortion ) = (6.02 n + 1.76) db thus for an 8-bit converter, this is 50 db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the ad7827 it is defined as: thd ( db ) = 20 log v 2 2 + v 3 2 + v 4 2 + v 5 2 + v 6 2 v 1 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is deter- mined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation terms are those for which neither m nor n are equal to zero. for example, the sec- ond order terms include (fa + fb) and (fa C fb), while the third order terms include (2fa + fb), (2fa C fb), (fa + 2fb) and (fa C 2fb). the ad7827 is tested using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second and third order terms are of dif- ferent significance. the second order terms are usually dis- tanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input fre- quencies. as a result, the second and third order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dbs. relative accuracy relative accuracy or endpoint nonlinearity is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this is the deviation of the 128th code transition (01111111) to (10000000) from the ideal, i.e., v ref /2 (v dd = 5 v), 0.8 v ref /2 (v dd = 3 v). zero scale error this is the deviation of the first code transition (00000000) to (00000001) from the ideal, i.e., v ref /2 C1.25 v + 1 lsb (v dd = 5 v 10%), or 0.8 v ref /2 C1.0 v + 1 lsb (v dd = 3 v 10%). full-scale error this is the deviation of the last code transition (11111110) to (11111111) from the ideal, i.e., v mid + 1.25 v C 1 lsb (v dd = 5 v 10%), or v mid + 1.0 v C 1 lsb (v dd = 3 v 10%). gain error this is the deviation of the last code transition (1111 . . . 110) to (1111 . . . 111) from the ideal, i.e., v ref C 1 lsb, after the offset error has been adjusted out. track/hold acquisition time track/hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within 1/2 lsb, after the point at which the track/hold returns to track mode. this happens approximately 120 ns after the falling edge of convst . it also applies when there is a step input change on the input voltage applied to the v in input of the ad7827. it means that the user must wait for the duration of the track/hold acquisition time after the end of conversion or after a step input change to v in before starting another conversion, to ensure that the part operates to specification.
ad7827 C6C rev. 0 circuit description the ad7827 consists of a track-and-hold amplifier followed by a half-flash analog-to-digital converter. this device uses a half- flash conversion technique where one 4-bit flash adc is used to achieve an 8-bit result. the 4-bit flash adc contains a sampling capacitor followed by 15 comparators that compare the un known input to a reference ladder to get a 4-bit result. this first flash, i.e., coarse conversion, provides the 4 msbs. for a full 8-bit reading to be realized, a second flash, i.e., a fine conversion, must be performed to provide the 4 lsbs. the 8-bit word is then placed in the serial shift register. figures 2 and 3 below show simplified schematics of the adc. when the adc starts a conversion, the track-and-hold goes into hold mode and holds the analog input for 120 ns. this is the acquisition phase as shown in figure 2 when switch 2 is in position a. at the point when the track-and-hold returns to its track mode, this signal is sampled by the sampling capacitor as switch 2 moves into position b. the first flash occurs at this instant and is then followed by the second flash. typically the first flash is complete after 100 ns, i.e., at 220 ns, while the end reference decode logic output register output driver . . . . timing and control logic hold sw2 b a sampling capacitor r16 r15 r14 r13 r1 15 14 13 1 t/h d out v in figure 2. adc acquisition phase reference decode logic output register output driver . . . . timing and control logic hold sw2 b a sampling capacitor r16 r15 r14 r13 r1 15 14 13 1 t/h d out v in figure 3. adc conversion phase of the second flash, and hence the 8-bit conversion result, is available at 330 ns. as shown in figure 4 the track-and-hold returns to track mode after 120 ns, and so starts the next acqui- sition before the end of the current conversion. figure 6 shows the adc transfer function. 120ns t 1 t 2 t 3 t 7 t 8 t 4 t 10 hold hold track track 12345678 db7 db6 db5 db4 db3 db2 db1 db0 convst rfs sclk d out figure 4. track-and-hold timing typical connection diagram figure 5 shows a typical connection diagram for the ad7827. the serial interface is implemented using three wires; the rfs is a logic output and the serial clock is continuous. the receive frame sync signal (rfs) idles high, the falling edge of convst initiates a conversion and the first rising edge of the serial clock after the end of conversion causes the rfs signal to go low. this falling edge of rfs is used to drive the rfs on a micro- processorsee serial interface section for more details. v ref is connected to a voltage source such as the ad780, while v dd is connected to a voltage source of 3 v 10% or 5 v 10%. due to the proximity of the convst and v in pins, it is recom- mended to use a 10 nf decoupling capacitor on v in . when v dd is first connected the ad7827 powers up in a low cu rrent mode, i.e., power-down. a rising edge on the convst pin will cause the ad7827 to fully power up. for applications where power consumption is of concern, the automatic power-down at the end of a conversion should be used to improve power perfor- mance. see the power-down options section of this data sheet. m c/ m p 0.1 m f 10 m f 2.5v ad780 three-wire serial interface 0v to 2.5v (v dd = 5v) 0v to 2v (v dd = 3v) input supply +3v 6 10% or +5v 6 10% sclk d out rfs convst v dd v ref v in gnd ad7827 figure 5. typical connection diagram
ad7827 C7C rev. 0 adc transfer function the output coding of the ad7827 is straight binary. the designed code transitions occur at successive integer lsb values (i.e., 1 lsb, 2 lsbs, etc.). the lsb size is = v ref /256 (v dd = 5 v) or the lsb size = (0.8 v ref )/256 (v dd = 3 v). the ideal transfer characteristic for the ad7827 is shown in figure 6 below. (v dd = 5v) 1lsb = v ref /256 (v dd = 3v) 1lsb = 0.8v ref /256 1lsb (v dd = 5v) v ref /2 (v dd = 3v) 0.8v ref /2 v ref /2+1.25v C 1lsb 0.8v ref /2+1v C 1lsb (v dd = 5v) v ref /2 C 1.25v (v dd = 3v) 0.8v ref /2 C 1v 11111111 111....110 111....000 10000000 000....111 000....010 000....001 00000000 adc code figure 6. transfer characteristic analog input the ad7827 has a single input channel with an input range of 0 v to 2.5 v or 0 v to 2.0 v, depending on the supply voltage (v dd ). this input range is automatically set up by an on-chip v dd detector circuit. 5 v operation of the adc is detected when v dd exceeds 4.1 v and 3 v operation is detected when v dd falls below 3.8 v. this circuit also possesses a degree of glitch rejection; for example, a glitch from 5.5 v to 2.7 v up to 60 ns wide will not trip the v dd detector. note: although there is a v ref pin from which a voltage refer- ence of 2.5 v may be sourced, or to which an external reference may be applied, this does not provide an option of varying the value of the voltage reference. as stated in the specifications for the ad7827, the input voltage range at this pin is 2.5 v 2%. analog input structure figure 7 shows an equivalent circuit of the analog input struc- ture of the ad7827. the two diodes, d1 and d2, provide esd protection for the analog inputs. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 200 mv. this will cause these diodes to become forward biased and start conducting current into the substrate. the maximum current these diodes can conduct without caus- ing irreversible damage to the part is 20 ma. the capacitor c2 in figure 7 is typically about 4 pf and can mostly be attributed to pin capacitance. the resistor r1 is a lumped component made up of the on resistance of several components including that of the multiplexer and the track-and-hold. this resistor is typically about 310 w . the capacitor c1 is the track-and-hold capacitor and has a capacitance of 0.5 pf. switch 1 is the track- and-hold switch, while switch 2 is that of the sampling capaci- tor as shown in figures 2 and 3. when in track phase, switch 1 is closed and switch 2 is in position a. when in hold mode, switch 1 opens while switch 2 remains in position a. the track-and-hold remains in hold mode for 120 nssee circuit description, after which it returns to track mode and the adc enters its conversion phase. at this point switch 1 opens and switch 2 moves to position b. at the end of the conversion switch 2 moves back to position a. v dd v in d1 r1 310 v d2 sw1 c1 0.5pf a b sw2 c2 4pf figure 7. equivalent analog input circuit the on-chip track-and-hold can accommodate input frequen- cies to 10 mhz, making the ad7827 ideal for subsampling applications. when the ad7827 is converting a 10 mhz input signal at a sampling rate of 1 msps, the effective number of bits typically remains above seven corresponding to a signal-to- noise ratio of 42 dbs as shown in figure 8. input frequency C mhz 50 38 0.2 10 134 568 48 46 44 42 40 f sample = 1mhz snr C db figure 8. snr vs. input frequency on the ad7827
ad7827 C8C rev. 0 power-up times the ad7827 has a 1 m s power-up time when using an external reference and a 25 m s power-up time when using the on-chip reference. when v dd is first connected, the ad7827 is in a low current mode of operation. in order to carry out a conversion the ad7827 must first be powered up. the ad7827 is pow- ered up by a rising edge on the convst pin and a conversion is initiated on the falling edge of convst . figure 9 shows how to power up the ad7827 when v dd is first connected or after the adc has been powered down using the convst pin when using either the on-chip, or an external, reference. when using an external reference the falling edge of convst may occur before the required power-up time has elapsed; however, the conversion will not be initiated on the falling edge of convst but rather at the moment when the part has com- pletely powered up, i.e., after 1 m s. if the falling edge of convst occurs after the required power-up time has elapsed, it is upon this falling edge that a conversion is initiated. when using the on-chip reference, it is necessary to wait the required power-up time of approximately 25 m s before initiating a con- version, i.e., a falling edge on convst may not occur before the required power-up time has elapsed, when v dd is first con- nected or after the ad7827 has been powered down using the convst pin as shown in figure 9. external reference on-chip reference conversion initiated here conversion initiated here v dd convst v dd convst t power-up 1 m s t power-up 25 m s figure 9. power-up time power vs. throughput superior power performance can be achieved by using the automatic power-down (mode 2) at the end of a conversion (see operating modes section of this data sheet). figure 10 shows how the automatic power-down is implemented using the convst signal to achieve the optimum power per- formance for the ad7827. the duration of the convst pulse is set to be equal to or less than the power-up time of the de- vices (see operating modes section). as the throughput rate is reduced, the device remains in its power-down state for longer and the average power consumption over time drops accordingly. for example, if the ad7827 is operated in a continuous sam- pling mode, with a throughput rate of 100 ksps and using an external reference, the power consumption is calculated as follows. the power dissipation during normal operation is 30 mw, v dd = 3 v. convst t power-up 1 m s t convert 330ns power-down t cycle 10 m s @ 100ksps figure 10. automatic power-down if the power-up time is 1 m s and the conversion time is 330 ns (@ 25 c), the ad7827 can be said to dissipate 30 mw for 1.33 m s (worst case) during each conversion cycle. if the throughput rate is 100 ksps, the cycle time is 10 m s and the average power dissipated during each cycle is (1.33/10) (30 mw) = 3.99 mw. figure 11 shows the power vs. throughput rate for automatic full power-down. throughput C ksps 100 10 0.1 0 500 50 100 150 200 250 300 350 400 450 1 power C mw figure 11. power vs. throughput frequency C hz 0 C40 C80 0 500 50 db 100 150 200 250 300 350 400 450 C10 C20 C60 C70 C30 C50 2048 point fft sampling 1msps f in = 30khz figure 12. ad7827 snr
ad7827 C9C rev. 0 operating modes the ad7827 has two possible modes of operation depending on the state of the convst pulse at the end of a conversion. mode 1 operation (high speed sampling) when the ad7827 is operated in mode 1 the device is not powered down between conversions. this mode of operation allows high throughput rates to be achieved. figure 13 shows how this optimum throughput rate is achieved by bringing convst high before the end of the conversion. when operat- ing in this mode, a new conversion should not be initiated until 30 ns after the end of a read operation. this is to allow the track/hold to acquire the analog signal to 0.5 lsb accuracy. mode 2 operation (automatic power-down) when the ad7827 is operated in mode 2 (see figure 14) it automatically powers down 530 ns after the falling edge of convst . the convst signal is brought low to initiate a conversion and is left logic low until 530 ns has elapsed after the falling edge of the convst pulse, i.e., before point a or point b in figure 14, depending on the actual value of t 2 (see timing characteristics). the state of the convst signal is sampled at this point (i.e., 530 ns after convst falling edge) and the ad7827 will power down as long as the convst is low. the adc is powered up again on the rising edge of the convst signal. the convst pulse width does not have to be as long as the power-up time if an external reference is used (see power-up times section). superior power performance can be achieved in this mode of operation by powering up the ad7827 to only carry out a conversion. the serial interface of the ad7827 is still fully operational while the device is powered down. t 2 t 1 current conversion result convst rfs sclk d out figure 13. mode 1 operation timing diagram t 2 current conversion result convst rfs sclk d out t power-up a b figure 14. mode 2 operation timing diagram
ad7827 C10C rev. 0 ad7827 serial interface in order to achieve a high throughput rate, the serial port of the ad7827 has been optimized for high speed serial protocols. many high speed serial protocols use a continuous serial clock to transfer data, e.g., the serial ports of many popular dsps like the tms320c5x, adsp-21xx and dsp560xx. the serial inter- face of the ad7827 is optimized for communication with such devices. the serial interface of the ad7827 uses a three-wire interface to communicate with a master. the serial clock pin (sclk) is a logic input and determines the bit transfer rate. the receive frame synchronization pin (rfs) is a logic output and used to synchronize the data with a continuous serial clock. the data output pin (d out ) is a logic output and serial data is shifted out onto this pin on the rising edge of the serial clock. the first rising edge of the serial clock after the end of a con version causes the rfs pin to go logic low. (see figure 15 below.) the d out pin leaves its high impedance state and the first msb is shifted out on the first sclk rising edge after the end of conv ersion. the remaining seven data bits are shifted out on subsequent sclk rising edges. the d out pin enters its high impedance state again on the falling edge of the eighth sclk after rfs goes low. the rfs output goes high again on the rising edge of the ninth sclk. if the ad7827 does not receive a ninth sclk, the rfs will be reset logic high by the next falling edge of convst . db7 db6 db5 db4 db3 db2 db1 db0 rfs sclk d out convst t 1 t 2 t 3 t 7 t 8 t 4 t 10 12345678 t 9 t 5 t 11 t 6 figure 15. serial timing
ad7827 C11C rev. 0 microprocessor interfacing the serial interface on the ad7827 allows the part to be con- nected directly to a range of many different microprocessors and microcontrollers. this section explains how to interface the ad7827 with some of the more common dsp serial interface protocols. ad7827 to tms320c5x the serial interface on the tms320c5x uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices such as the ad7827. a receive frame synchronization output has been supplied on the ad7827 to allow easy interfacing with no extra gluing logic. the serial port of the tms320c5x is set up to operate in burst mode with internal clkx (tx serial clock) and fsr (rx frame sync). the serial port control register (spc) must have the following setup: f0 = 1, fsm = 1, mcm = 1. the connec- tion diagram is shown in figure 16. tms320c5x* clkx clkr dr fsr ad7827* sclk d out rfs *additional pins omitted for clarity figure 16. interfacing to the tms320c5x ad7827 to adsp-21xx the adsp-21xx family of dsps are easily interfaced to the ad7827 without the need for any extra gluing logic. the sport is operated in alternate framing mode. the sport control register should be set up as follows: tfsw = rfsw = 1, alternate framing invrfs = invtfs = 1, active low frame signal dtype = 00, right justify data slen = 0111, 8-bit data words isclk = 1, internal serial clock tfsr = rfsr = 1, frame every word irfs = 0, external framing signal itfs = 1, internal framing signal the 8-bit data words will be right justified in the 16-bit serial data registers when using this configuration. figure 17 shows the connection diagram. adsp-21xx* dr ad7827* sclk d out rfs rfs sclk *additional pins omitted for clarity figure 17. interfacing to the adsp-21xx ad7827 to dsp56xxx the connection diagram in figure 18 shows how the ad7827 can be connected to the ssi (synchronous serial interface) of the dsp56xxx family of dsps from motorola. the ssi is oper- ated in synchronous mode (syn bit in crb = 1) with inter- nally generated 1-bit clock period frame sync for both tx and rx (fsl1 and fsl0 bits in crb = 1 and 0 respectively). dsp56xxx* srd ad7827* sclk d out sc2 rfs sclk *additional pins omitted for clarity figure 18. interfacing to the dsp56xxx microcontrollers the ad7827 may also be interfaced to many microcontrollers, as a continuous serial clock is not essential. however, enough time must be left for the conversion to be complete before applying a burst of serial clocks to read out the data.
ad7827 C12C rev. 0 outline dimensions dimensions shown in inches and (mm). c3215C8C1/98 printed in u.s.a. 8-lead plastic dip (n-8) 8 14 5 0.430 (10.92) 0.348 (8.84) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 8-lead small outline package (so-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 4 1 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45

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